Molly Rocket

[Won]

Looks like the paper is out:

http://portal.acm.org/citation.cfm?doid=1360612.1360617

Unfortunately, it requires ACM membership, or being/knowing someone at Intel or RAD (who probably have already seen this stuff beforehand).

Some interesting information here. Apropos to SVT, the paper mentions handling page faults, but doesn't really describe the mechanism (Pentium-like?). I wonder if this feature could be hijacked to help SVT. It would also be really sweet if Larrabee's DX/OGL implementations were open-source, fostering hackability. That would be the Mutt's Nuts.*

I'm also pretty psyched about the notion of Larrabee native code. It seems like it has much potential, beyond the typical GPU/GPGPU stuff. I wish the paper went into a bit more detail about the execution environment on Larrabee. It is interesting that you can do I/O on Larrabee, that is proxied by the main processor/OS. What does software look like on Larrabee? It sounds like there is paging, but I wonder how closely Larrabee resembles a Pentium. Is there memory protection? Rings? Segmentation?

* I think you have to be Casey to say things like this and not sound foolish.

[NocturnDragon]

http://softwarecommunity.intel.com/articles/eng/3803.htm here you can find the paper without needing ACM membership.

http://softwarecommunity.intel.com/UserFiles/en-us/File/larrabee_manycore.pdf

[sean]

It doesn't look to me like Larrabee offers anything too exciting for SVT, because of its use of dedicated texture filtering hardware which is responsible for mipmapping and anisotropic filtering and everything, which means it's going to do all the address generation itself. So I think you'd have to implement SVT exactly the same as you do on every other GPU.

[soal]

I personally can't wait until games are released that run entirely on larrabee. It'd be a sweet demoscene!

[Won]

[ryg]

[sean]

It's certainly true that if you can generate texture in response to page faults, you have an opportunity to do something a little clever there if you're procedural. And for disk streaming, you might be able to use the page faulting to retry with a different mip-level and flag that a given page needs to be swapped in.

But I think that's more interesting if you have < 4GB of texture; SVT is interesting partially because it enables more larger than 64k x 64k texel textures. But that means you still need a >32-bit address mapping, which I assume Larrabee doesn't have (because why would it need it).

Maybe there's something clever you can do because you can write from the shader, like, when you discover you don't have the right mipmap, search up the tree for the one that's in memory, and then store that result into a cache. (My posted SVT code does stores that information in the page texture itself, but it only propogates it down a few levels to avoid needing to update e.g. 64 x 64 worth of blocks all pointing to the texture 6 levels above. A regular shader can work around that by searching up the tree for a non-empty page, but can't cache the result.)

But even though you can do that cacheing in a lock-free way (if any other thread is doing the same thing at the same time, it'll compute the exact same thing, so everyone can just write and who cares), it actually doesn't quite work (because you now need to clear that cache if a higher-res still-wrong-mipmap-level becomes available), which is back to the original problem. Maybe there's a trick here I'm not thinking of, so maybe something can be done, but it doesn't feel huge overall.

[casey]

[sean]

Also, I find it interesting that Intel is publishing this paper at all... as far as I know ATI and NVIDIA haven't been publishing equivalent papers about how GPUs work, have they?

I know there's been a lot of work reverse-engineering and reading patents to figure out what they do, though. Actually I was a little surprised to see the constant references in the paper to what they do, since I wasn't sure there was any public information Intel could reliably cite.

[casey]

[Won]

[jeffatrad]

Obviously, there is a ton that I'd like to say about Larrabee, but I can't. I will say that it's going to be awesome, though, and I think it will change lots of stuff.

->Jeff

[Zaphos]

I imagine the Stanford people on the paper would also have pushed for publishing the results. Also, it's probably helpful to Intel if they can get the research community thinking about new things that can be done with The Unique Power of Larrabee ...

[Zaphos]

Also -- thank you for the link, Won!

And, does anyone know if this exists yet (from the paper's references):

BADER, A., CHHUGANI, J., DUBEY, P., JUNKINS, S., MORRISON T.,
RAGOZIN, D., SMELYANSKIY. 2008. Game Physics Performance
On Larrabee Architecture. Intel whitepaper, available in
August, 2008. Web site: techresearch.intel.com.

... I know there's a link right there, but I can't find anything on that site. *cry*

[TomF]